National Instruments PCI-1200 Instrukcja Użytkownika Pobierz pdf (Strona 55)

Chapter 4 Theory of Operation

The PCI-1200 generates an interrupt in the following five cases (each of

these interrupts is individually enabled and cleared):

• When a single A/D conversion can be read from the A/D FIFO

memory.

• When the A/D FIFO is half-full.

• When a DAQ operation completes, including when either an

OVERFLOW or an OVERRUN error occurs.

• When the digital I/O circuitry generates an interrupt.

• When a rising edge signal is detected on the DAC update signal.

Timing

The PCI-1200 uses two 82C53 counter/timer integrated circuits for internal

DAQ and DAC timing and for general purpose I/O timing functions.

Figure 4-3 shows a block diagram of both groups of timing circuitry

(counter groups A and B).

1 2 ... 50 51 52 53 54 55 56 57 58 59 60 ... 99 100

Brak uwag

National Instruments PCI-1200 Instrukcja Użytkownika Strona 55