National Instruments Deterministic Ethernet Expansion Chassis NI 9144 Instrukcja Użytkownika Pobierz pdf (Strona 50)

NI 9144 User Guide and Specifications 50 ni.com

Where:

Turbo Disab le

0 The conversion rate is equal to the

oversample clock rate/128.

Set to 0 for conversion rates > 25 kS/s.

1 The conversion rate is equal to the

oversample clock rate/256.

Set to 1 for conversion rates < 25 kS/s.

Clock Divisor

The clock source (internal or external) is divided by this value and used

as the converters’ oversample clock. Valid values are from 2 to 31, but

the final divided clock must be between 512 kHz and 6.4 MHz. This

means that only values from 2 to 25 are valid when using the 12.8 MHz

internal clock source.

Clock Source

0b00 = 0 The OCLK pin is used as the

oversample clock source.

0b01 = 1 The 12.8 MHz internal clock is

used as the clock source and this

12.8 MHz is driven onto the

OCLK

pin.

0b10 = 2 The internal clock is used but not

driven onto

OCLK pin. Currently,

this is the required clock setting.

0b11 = 3 Reserved.

Table 44. NI 9233 Calibration Data

Data Rate

Turbo

Disable

Clock

Divisor

Clock

Source

Configure

ADC

Oversample

Clock Rate

50.000 kS/s 0 00010 10 0x0A 6.40 MHz

25.000 kS/s 1 00010 10 0x8A 6.40 MHz

12.500 kS/s 1 00100 10 0x92 3.20 MHz

1 2 ... 45 46 47 48 49 50 51 52 53 54 55 ... 64 65

Brak uwag

National Instruments Deterministic Ethernet Expansion Chassis NI 9144 Instrukcja Użytkownika Strona 50